EELE 414 - Introduction to VLSI Design
(Fall 2015, updated 12/03)
Course Description
This course introduces students to the fundamentals concepts of CMOS VLSI circuit design. This course will cover CMOS device characteristics and timing. CMOS fabrication will be covered including process steps, metal, active, and poly layers, and design rules. CAD tools will be introduced for use in design, simulation, and layout of integrated circuits. Design analysis techniques will be presented for the static and dynamic evaluation of CMOS circuits. Combinational & Sequentual logic design will be presented in addition to semiconductor memory technology. (Syllabus)
Textbook
"CMOS Digital Integrated Circuits" 3rd Edition. by Sung-Mo Kang and Yusuf Leblebici; McGraw Hill, 2003.
Time & Location
Cobleigh Hall 632
Tuesday, Thursday
11:00am - 12:15pm
Pre-Requisites
- EE262 - Logic Circuits Lab
- EE317 - Electronics
Weekly Schedule
| Day | Date | Topic | Read | Assignments |
|---|---|---|---|---|
| T | 8/26 | M1: Economy (Intro, Design Techniques) | 1.1-1.10 | |
| R | 8/28 | M2: MOSFETS (Device Physics) | 3.1 | |
| T | 9/2 | M2: MOSFETS (Structure) | 3.2-3.3 | |
| R | 9/4 | M2: MOSFETS (IV Characteristics) | 3.4 | |
| T | 9/9 | M2: MOSFETS (Scaling) | 3.5 | HW#1 due |
| R | 9/11 | M2: Lab (COB 601), DC sims Tanner T-SPICE | - | |
| T | 9/16 | M2: Lab (COB 601), TRAN sims Tanner T-SPICE | 3.6 | HW #2 due |
| R | 9/18 | M2: MOSFETS (Capacitance) | - | |
| T | 9/23 | M3: SPICE | Ch.4 | HW #3 due |
| R | M3: Lab (COB 601), Models & Exam Review | - | ||
| T | 9/30 | M4: CMOS Fabrication Process | - | |
| R | 10/2 | M4: CMOS Fabrication Process & Physical Design w Ledit | 2.1-2.3 | |
| T | 10/7 | 2.4-2.5 | ||
| R | 10/9 | - | ||
| T | 10/14 | M5: Inverter - Static Characteristics | - | |
| R | 10/16 | M5: Inverter - Static Characteristics | 5.1-5.4 | |
| T | 10/21 | M5: Inverter - Static Characteristics | - | |
| R | 10/23 | M5: Inverter - Static Characteristics | 6.1-6.7 | |
| T | 10/28 | M5: Inverter - Switching Characteristics | - | HW #4 due |
| R | 10/30 | M5: Inverter - Switching Characteristics | - | |
| T | 11/4 | M5: Inverter - Switching Characteristics | - | |
| R | 11/6 | Exam #2 | - | |
| T | 11/11 | M6: Combinational Logic | 7.1-7.3 | |
| R | 11/13 | M6: Combinational Logic | 7.4-7.5 | |
| T | 11/18 | No Class, Thanksgiving | - | - |
| R | 11/20 | No Class, Thanksgiving | - | - |
| T | 11/25 | M7: Sequential Logic | 8.1-8.5 | |
| R | 11/27 | Memory (SRAM) | 10.1, 10.3 | |
| T | 12/2 | Memory (DRAM) | 10.2, 10.4 | - |
| R | 12/4 | Memory (FLASH) | 10.5 | - |
| R | 12/8 | Exam #3 (12:00pm - 1:50pm) | - | - |
Course Handouts
- Syllabus (PDF)
- Guide to Tanner EDA Tools (S-edit, T-PSPICE, L-edit) (PDF)
- Corrections to the Guide to Tanner EDA Tools (S-edit, T-PSPICE, L-edit)(PDF)
- Libraries & Models for Tanner EDA Tools (Generic 0.25um Kit) (zip)
- IEEE Journal Paper Template (doc)
Lecture Notes
- Module 1: VLSI Economy (PPTX) (PDF)
- Module 2: MOSFETs (PPTX) (PDF)
- Module 3: SPICE (PPTX) (PDF)
- Module 4: CMOS Fab (PPTX) (PDF)
- Module 5: CMOS Inverters (PPTX) (PDF)
- Module 6: Combinational Logic (PPTX) (PDF)
Homework Problems
- Homework 1: VLSI Economy (PDF)
- Homework 2: MOSFET Operation (due 9/18) (PDF)
- Homework 3: NMOS/PMOS IV Characteristics (w/ DC sim) (PDF)
- Homework 4: MOS Capacitance (w/ AC sim) Due: 10/28 (PDF)
- Homework 5: CMOS Inverter Static Characteristics, VTC (w/ DC sim) Due: 12/2 (PDF)
Homework Solutions (password: 41414)
- Homework 01 solution: VLSI Economy (PDF)
- Homework 02 solution: MOSFET Operation (PDF)
- Homework 03 solution: NMOS/PMOS IV Characteristics (w/ DC sim) (PDF)
- Homework 04 solution: MOS Capacitance (w/ AC sim) (PDF)