Machine Learning-Inspired Manycore Chip Design: Interconnect architecture to power management
- Thursday, February 22, 2018 from 11:00am to 11:50am
- Strand Union Building, Room 168 - view map
Over the years, advances in silicon fabrication techniques have made it possible to steadily increase the number of processing cores on a single chip. Today, these manycore chips provide the compute power and form factor to enable the next generation of high-performance computing systems necessary for various applications, starting from autonomous vehicles to smartphones to fog/cloud computing. However, with such a high degree of integration, we need to explore suitable design optimization and power management techniques. In this seminar I will discuss several challenges and solutions for designing high-performance and energy-efficient manycore chips. In particular, I will focus on how recent advances in machine learning can be utilized to create effective design optimization mechanisms suitable for manycore-based single-chip computing systems. We will also discuss how these manycore chips can be enablers for emerging big-data applications. We will conclude this seminar by discussing our current work on how machine learning is able to assist in designing 3D heterogeneous systems for deep learning and how machine learning could assist in other possible future design challenges of manycore systems.