LaMeres' Research Overview
Exploiting Reconfigurable Fabrics to Optimize Computing
Reconfigurable digital circuitry has always provided inherent design flexibility. Historically, this flexibility has come at the expense of performance. However, with advances in IC fabrication technology, programmable logic performance has advanced to the point where it is meeting the computation needs of modern applications. This has created a paradigm shift in the way digital circuitry can be implemented. If programmable logic cells can perform as well as dedicated IC blocks, then the standard VLSI design flow will need to be reinvented. Reprogrammable fabrics now have the capacity to contain not only custom hardware but multiple soft processor cores. This capability enables computing approaches such as single-chip hardware accelerated processors, dynamically scalable parallel processing, and reconfigurable computing. The capability that now exists in computing hardware makes the effective partitioning between hardware and software a difficult challenge due to the endless implementation possibilities.
Reconfigurable fabrics also have enabled novel architectures to address the robustness of a computer system. Redundancy (both static and dynamic) can be used to detect and recover from faults and spatial avoidance of faults can be used to extend lifetime of a part. These opportunities for fault tolerance are of great interest to the military and aerospace industry due to their unique need for robust computing platforms.
Currently, research is being conducted in the ECE department at MSU in the area of effective hardware/software partitioning using soft processors on FPGAs. Research is also being conducted on the design of a radiation tolerant computing system for the aerospace industry which exploits partial reconfiguration of an FPGA to spatially move soft processors to different locations on the FPGA in order to avoid radiation strikes. Reconfiguration is also used to dynamically recover from a non-damaging radiation strike.
The picture shown here is a Radiation Tolerant Many Core Computing System implemented on a Xilinx Artix-7 FPGA. This system was developed for NASA to help increase reliability in interplanetary flight systems. This system contains 16 soft processors. At any given time, 3 of the processors are used in Triple Modular Redundancy (TMR) to check for faults due to radiation. Upon a soft radiation strike, the TMR system reboots and resynchronizes the faulted processors. If the fault occurs in the reconfiguration RAM of the FPGA, the system performs partial reconfiguration on the effected processor in order to recover. If the fault is unrecoverable, the system brings on a new spare processor to form the TMR configuration and marks the damaged area as unusable.
Below are two missions that have been conducted to demostrate the radiation tolerant computer technology.
Radiation Tolerant computer Mission on the International SpaceStation
(RTcMISS) pronouned Artemis (art-eh-miss)
Shown here is an implementation of the Radiation Tolerant Computer in a form factor that allowed testing onboard the International Space Station. During 2017, RTcMISS spend 12 months on the ISS where it collected data on how well the computer architecture responded to space radiation. RTcMISS was returned to MSU in 2018 and is currently undergoing additional examination.
RadSat-g - Radiation Tolerant Computer Experiment, Satellite Mission
Shown here is the 3U small satellite developed at MSU to carry the radiation tolerant computing technology in a stand-alone mission in Low Earth Orbit (LEO). The satellite was carried to the ISS in March of 2018 onboard the Orbital ATK OA9 ISS ressupply mission. It was then put into orbit in July of 2018 using the NanoRacks CubeSat deployer. RadSat-g is currently orbiting Earth where it is collecting data on how well the computer architecture responds to space radiation. Data is downlinked to the MSU ground station during each acceptable pass (~1-2 times per week).