Textbook Cover

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Textbook Videos

Chapter 1: Analog Vs. Digital

1.1: Differences Between Analog & Digital Systems

- Analog vs. Digital _{(11 min)}

1.2: Advantages of Digital over Analog Systems

- Advantages / Disadvantages _{(15 min)}

Chapter 2: Number Systems

2.1: Positional Number Systems

- Formation & Terminology _{(24 min)}

2.2: Base Conversions

- Converting to Decimal _{(14 min)}
- Converting from Decimal _{(12 min)}
- Converting between powers-of-2 Bases _{(3 min)}

2.3: Binary Arithmetic

- Binary Arithmetic _{(13 min)}

2.4: Unsigned and Signed Numbers

- Unsigned Numbers _{(6 min)}

- Signed Numbers _{(21 min)}

- Two's Complement Arithmetic _{(11 min)}

Chapter 3: Digital Circuitry & Interfacing

3.1: Basic Gates

- Functional Description of Digital Logic Behavior _{(13 min)}

- BUF, INV, AND, NAND, OR, NOR Gates _{(11 min)}

- XOR, XNOR Gates _{(8 min)}

3.2: Digital Circuit Operation

- Logic Levels & DC Specifications _{(19 min)}

- Power Supplies & Maximum Current Specifications _{(22 min)}

- Switching Characteristics _{(10 min)}

- Datasheets _{(21 min)}

3.3: Logic Families

- Logic Family Overview, Fan-In, Fan-Out _{(14 min)}

- CMOS Overview _{(30 min)}

- CMOS Inverter _{(14 min)}

- CMOS NAND Gate _{(17 min)}

- CMOS NOR Gate _{(6 min)}

- TTL Overview _{(11 min)}

- 7400 Logic Series Overview _{(13 min)}

3.4: Driving Loads

- Driving Other Gates _{(6 min)}

- Driving Resistors _{(12 min)}

- Driving LEDs _{(14 min)}

Chapter 4: Combinational Logic Design

4.1: Boolean Algebra

- Introduction & Axioms _{(14 min)}

- Single-Variable Theorems _{(20 min)}

- Multiple-Variable Theorems _{(22 min)}

- Functionally Complete Sets _{(6 min)}

4.2: Combinational Logic Analysis

- Analysis Overview _{(13 min)}

4.3: Combinational Logic Synthesis

- SOP & Minterms _{(15 min)}

- Minterm Lists _{(5 min)}

- SOP Design Example _{(8 min)}

- POS & Maxterms _{(11 min)}

- Maxterm Lists _{(3 min)}

- POS Design Example _{(10 min)}

4.4: Logic Minimization

- Algebraic Minimization _{(6 min)}

- Karnaugh Map Formation _{(19 min)}

- Minimized SOP's using K-maps _{(21 min)}

- Minimized POS's using K-maps _{(17 min)}

- Minimal Sums _{(8 min)}

- Don't Cares _{(7 min)}

- XOR/XNOR Patterns in K-maps _{(5 min)}

4.5: Timing Hazards & Glitches

- Hazard Overview _{(15 min)}

Chapter 5: VHDL (part 1)

5.1: History of HDLs

- History _{(19 min)}

5.2: HDL Abstraction

- Abstraction _{(17 min)}

5.3: The Modern Digital Design Flow

- Modern Digital Design _{(10 min)}

5.4: VHDL Constructs

- Constructs _{(26 min)}

5.5: Modeling Concurrent Functionality in VHDL

- Modeling Techniques _{(26 min)}

- Downloading ModelSim for Functional Simulations _{(5 min)}

- Simulation Example: Getting Started with ModelSim - AND3.vhd _{(9 min)}

- Simulation Example: Concurrent Signal Assignments w/ Logical Operators _{(11 min)}

- Simulation Example: Conditional Signal Assignments _{(7 min)}

- Simulation Example: Selected Signal Assignments _{(9 min)}

5.6: Structural Design in VHDL

- Components _{(11 min)}

5.7: Overview of Simulation Test Benches

- Test Bench Overview _{(4 min)}

Chapter 6: MSI Logic

6.1: Decoders

- Decoder Design by Hand _{(12 min)}

- Decoder Modeling in VHDL _{(7 min)}

6.2: Encoders

- Encoder Design by Hand _{(10 min)}

- Encoder Modeling in VHDL _{(6 min)}

6.3: Multiplexers

- Multiplexer Design by Hand _{(13 min)}

- Multiplexer Modeling in VHDL _{(4 min)}

6.4: Demultiplexers

- Demultiplexer Design by Hand _{(10 min)}

- Demultiplexer Modeling in VHDL _{(5 min)}

Chapter 7: Sequential Logic

7.1: Sequential Logic Storage Devices

- Cross Coupled Inverter Pair & Metastability _{(20 min)}

- SR Latch _{(12 min)}

- S'R' Latch _{(9 min)}

- SR Latch w/ Enable _{(9 min)}

- D Latch _{(6 min)}

- D-flip-flop _{(14 min)}

7.2: Sequential Logic Timing Considerations

- Sequential Logic Timing _{(10 min)}

7.3: Circuits Based on Sequential Storage Devices

- Toggle Flops _{(12 min)}

- Ripple Counters _{(14 min)}

- Switch Debouncing _{(20 min)}

- Shift Registers _{(3 min)}

7.4: Finite State Machine

- FSM Introduction & Descripting FSM Behavior _{(20 min)}

- FSM Synthesis _{(29 min)}

- FSM Design Process Overview _{(6 min)}

- FSM Example: Sequence Detector _{(17 min)}

- FSM Example: Vending Machine _{(12 min)}

7.5: Counters

- Example: 2-bit Binary Up Counter _{(17 min)}

- Example: 2-bit Binary Up/Down Counter _{(8 min)}

- Example: 2-bit Gray Code Up Counter _{(7 min)}

- Example: 2-bit Gray Code Up/Down Counter _{(7 min)}

- Example: 3-bit One-Hot Up Counter _{(7 min)}

- Example: 3-bit One-Hot Up/Down Counter _{(6 min)}

7.6: FSM Reset Condition

- Reset Condition _{(7 min)}

7.7: Sequential Logic Analysis

- Functional Analysis of FSMs _{(9 min)}

- Timing Analysis of FSMs _{(15 min)}

Chapter 8 - VHDL (Part 1)

8.1: The Process

- Process Overview _{(26 min)}

8.2: Conditional Programming Constructs

- If/Then Statements _{(14 min)}

- Case Statements _{(22 min)}

- Loops _{(9 min)}

8.3: Signal Attributes

- Attributes Overview _{(6 min)}

8.4: Test Benches

- Test Bench Basics _{(23 min)}

- Test Bench Report & Assert Statements _{(26 min)}

8.5: Packages

- STD_LOGIC_1164 Overview _{(23 min)}

- STD_LOGIC_1164 In VHDL _{(9 min)}

- NUMERIC_STD + Misc Packages _{(13 min)}

- TEXTIO and Writing to External Files _{(15 min)}

- TEXTIO and Reading from External Files _{(19 min)}

Chapter 9 - Behavioral Modeling of Sequential Logic

9.1: Modeling Sequential Storage Devices in VHDL

- D-Flip-Flops using a Process _{(31 min)}

9.2: Modeling Finite-State-Machines in VHDL

- Overview of FSMs in VHDL using the 3-Process Approach _{(20 min)}

- FSM Modeling with User-Enumerated State Encoding (PBWC Ex) _{(15 min)}

- FSM Modeling with Explicit State Encoding w/ SubTypes (PBWC Ex) _{(9 min)}

9.3: FSM Design Examples in VHDL

- Serial Bit Sequence Detector _{(28 min)}- Vending Machine _{(15 min)}

9.4: Modeling Counters in VHDL

- Counters in VHDL w/ 1-Process and Integers/Type-Casts _{(19 min)}

- Counters in VHDL w/ Range Checking _{(25 min)}
- Counters in VHDL w/ Enables _{(5 min)}
- Counters in VHDL w/ Loads _{(17 min)}

9.5: RTL Modeling

- Registers w/ Enables _{(18 min)}
- Shift Registers _{(11 min)}
- Agents on a Multi-Drop Bus _{(21 min)}

Chapter 10 - Memory

10.1: Memory Architecture & Terminology

- Architecture & Terminology Overview _{(33 min)}

10.2: Non-Volatile Memory Technology

- Non-Volatile Memory Overview _{(33 min)}

10.3: Volatile Memory Technology

- SRAM _{(11 min)}- DRAM _{(17 min)}

10.4: Modeling Memory in VHDL

- Modeling ROM in VHDL _{(14 min)}
- Modeling R/W Memory in VHDL _{(7 min)}

Chapter 11 - Programmable Logic

11.1: Programmable Arrays

- Programmable Array Overview _{(24 min)}

11.2: Field Programmable Gate Arrays

- FPGA Overview _{(13 min)}

Chapter 12 - Arithmetic Circuits

12.1: Addition

- Ripple Carry Adders (RCA) _{(28 min)}

- RCA Timing _{(8 min)}

- RCA Structural Design in VHDL _{(5 min)}

- Carry Look Ahead Adders (CLA), CLA Timing _{(22 min)}

- Behavioral Modeling of Adders in VHDL _{(15 min)}

12.2: Subtraction

- Subtraction Overview _{(18 min)}

12.3: Multiplication

- Multiplication Overview _{(23 min)}

12.4: Division

- Division Overview _{(16 min)}

Chapter 13 - Computer Systems

13.1: Computer Hardware

- Computer System Overview _{(12 min)}

- Computer Hardware Overview _{(16 min)}

- Computer CPU & Memory Details _{(12 min)}

13.2: Computer Software

- Opcodes & Operands, Addressing Modes _{(16 min)}

- Instructions Classes: Loads _{(23 min)}

- Instructions Classes: Stores _{(11 min)}

- Instructions Classes: Data Manipulations _{(11 min)}

- Instructions Classes: Branches _{(14 min)}

13.3: Computer Implementation in VHDL: An 8-Bit Computer Example

- Memory System _{(22 min)}

- CPU: Data Path _{(22 min)}

- CPU: Control Unit - LDA_IMM Instruction _{(20 min)}

- CPU: Control Unit - LDA_DIR Instruction _{(9 min)}

- CPU: Control Unit - STA_DIR Instruction_{(16 min)}

- CPU: Control Unit - ADD_AB Instruction _{(8 min)}

- CPU: Control Unit - BRA Instruction _{(12 min)}

- CPU: Control United - BEQ Instruction _{(13 min)}

13.4: Architecture Considerations

- Von Neumann vs. Harvard _{(6 min)}

Lab Exercises

Lab Exercises (based on Analog Discovery 2 + Altera FPGA Board)

Lab Exercise Workbook - DE0-CV Version (updated 6/29/2019)
Lab Exercise Workbook - DE10-Lite Version (updated 5/12/2022)

Lab Exercise Workbook - DE10-Lite Version (updated 3/4/2023)

Overview Videos

Chapter 1: Analog vs. Digital

Lab 1.1 Overview: Intro to Lab Equipment & Blinking an LED with the AWG _{(30 min)}

Chapter 2: Number Systems

Lab 2.1 Overview: 2-Bit Counter with AWG and Logic Analysis _{(14 min)}

Chapter 3: Digital Circuits & Interfacing

Lab 3.1 Overview: Digital Circuit Operation _{(26 min)}

Chapter 4: Combinational Logic Design

Lab 4.1 Overview: Prime Number Detector using Canonical Forms (+ LED Driver) _{(26 min)}

Lab 4.2 Overview: Prime Number Detector using Minimized Forms (+ Buzzer) _{(16 min)}

Lab 4.3 Overview: 7-Segment Decoder (Discrete) _{(14 min)}

Chapter 5: VHDL (part 1)

Installing Quartus Prime Lite, ModelSim, and the MAX10 Drivers (March 2023)_{(32 min)}
Lab 5.1 Overivew: 4-Input, Prime Number Detector (VHDL + FPGA) _{(35 min)}

Chapter 6: MSI Logic

Lab 6.1 Overview: 4-Input, 7-Segment Display Decoder (VHDL + FPGA) _{(23 min)}

Chapter 7: Sequential Logic Design

Lab 7.1 Overivew : 4-Bit Ripple Counter & Switch Debouncing _{(24 min)}

Lab 7.2 Overview: FSM Design, 3-Bit Binary Up/Down Counter _{(14 min)}

Lab 7.3 Overview: 4-bit Binary, Up/Down Counter FSM (VHDL + FPGA) _{(30 min)}

Chapter 8: VHDL (part 2)

Lab 8.1 Overview: 7-Segment Decoder using a Process _{(9 min)}

Lab 8.2 Overview: Design Reuse and Binary Characters on the 7-Segment Display _{(9 min)}

Chapter 9: Behavioral Modeling in VHDL

Lab 9.1 Overview: Ripple Counter _{(19 min)}

Lab 9.2 Overview: Walking 1 FSM _{(9 min)}

Lab 9.3 Overview: Counters w/ 1-Process + 2-to-n Clock Divider _{(15 min)}

Lab 9.4 Overview: BCD Counter + Precision Clock Divider _{(25 min)}

Chapter 10: Memory

Lab 10.1 Overview: Read Only Memory System _{(5 min)}

Lab 10.2 Overview: Read/Write Memory System _{(18 min)}

Chapter 11: Programmable Logic

Lab 11.1 Overview: FPGA Details _{(19 min)}

Chapter 12: Arithmetic Circuits

Lab 12.1 Overview: Signed Adders _{(4 min)}

Lab 12.2 Overview: Unsigned Adders _{(9 min)}

Chapter 13: Computer Systems

Computer Project Overview _{(15 min)}

Computer Project - Part 1: VHDL Shell _{(31 min)}

Computer Project - Part 2: Simulation of 4x Basic Instructions _{(25 min)}

Computer Project - Part 3: FPGA Implementation of Basic Instructions _{(16 min)}

Computer Project - Part 4: Implementation of Additional Instructions _{(6 min)}