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Textbook Videos

Chapter 1: Analog Vs. Digital

1.1: Differences Between Analog & Digital Systems 
1.2: Advantages of Digital over Analog Systems
Advantages / Disadvantages (15 min)

Chapter 2: Number Systems

2.1: Positional Number Systems
Formation & Terminology (24 min)
2.2: Base Conversions
- Converting to Decimal (14 min)
- Converting from Decimal (12 min)
- Converting between powers-of-2 Bases (3 min)
2.3: Binary Arithmetic
Binary Arithmetic (13 min)
2.4: Unsigned and Signed Numbers
- Unsigned Numbers (6 min)
- Signed Numbers (21 min)
- Two's Complement Arithmetic (11 min)

Chapter 3: Digital Circuitry & Interfacing

3.1: Basic Gates
- Functional Description of Digital Logic Behavior (13 min)
- BUF, INV, AND, NAND, OR, NOR Gates (11 min)
- XOR, XNOR Gates (8 min)
3.2: Digital Circuit Operation
- Logic Levels & DC Specifications (19 min)
- Power Supplies & Maximum Current Specifications (22 min)
- Switching Characteristics (10 min)
- Datasheets (21 min)
3.3: Logic Families
- Logic Family Overview, Fan-In, Fan-Out (14 min)
- CMOS Overview (30 min)
- CMOS Inverter (14 min)
- CMOS NAND Gate (17 min)
- CMOS NOR Gate (6 min)
- TTL Overview (11 min)
- 7400 Logic Series Overview (13 min)
3.4: Driving Loads
- Driving Other Gates (6 min)
- Driving Resistors (12 min)
- Driving LEDs (14 min)

Chapter 4: Combinational Logic Design

4.1:  Boolean Algebra
- Introduction & Axioms (14 min)
- Single-Variable Theorems (20 min)
- Multiple-Variable Theorems (22 min)
- Functionally Complete Sets (6 min)
4.2: Combinational Logic Analysis
- Analysis Overview (13 min)
4.3: Combinational Logic Synthesis
- SOP & Minterms (15 min)
- Minterm Lists (5 min)
- SOP Design Example (8 min)
- POS & Maxterms (11 min)
- Maxterm Lists (3 min)
- POS Design Example (10 min)
4.4: Logic Minimization
- Algebraic Minimization (6 min)
- Karnaugh Map Formation (19 min)
- Minimized SOP's using K-maps (21 min)
- Minimized POS's using K-maps (17 min)
- Minimal Sums (8 min)
- Don't Cares (7 min)
- XOR/XNOR Patterns in K-maps (5 min)
4.5: Timing Hazards & Glitches
- Hazard Overview (15 min)

Chapter 5: VHDL (part 1)

5.1: History of HDLs
- History (19 min)
5.2: HDL Abstraction
- Abstraction (17 min)
5.3: The Modern Digital Design Flow
- Modern Digital Design (10 min)
5.4: VHDL Constructs
- Constructs (26 min)
5.5: Modeling Concurrent Functionality in VHDL
- Modeling Techniques (26 min)
- Downloading ModelSim for Functional Simulations (5 min)
- Simulation Example: Getting Started with ModelSim - AND3.vhd (9 min)
- Simulation Example: Concurrent Signal Assignments w/ Logical Operators (11 min)
- Simulation Example: Conditional Signal Assignments (7 min)
- Simulation Example: Selected Signal Assignments (9 min)
5.6: Structural Design in VHDL
- Components (11 min)
5.7: Overview of Simulation Test Benches
- Test Bench Overview (4 min)

Chapter 6: MSI Logic

6.1: Decoders
Decoder Design by Hand (12 min)
Decoder Modeling in VHDL (7 min)
6.2: Encoders
Encoder Design by Hand (10 min)
Encoder Modeling in VHDL (6 min)
6.3: Multiplexers
Multiplexer Design by Hand (13 min)
Multiplexer Modeling in VHDL (4 min)
6.4: Demultiplexers
Demultiplexer Design by Hand (10 min)
Demultiplexer Modeling in VHDL (5 min)

Chapter 7: Sequential Logic

7.1: Sequential Logic Storage Devices
Cross Coupled Inverter Pair & Metastability (20 min)
SR Latch (12 min)
S'R' Latch (9 min)
SR Latch w/ Enable (9 min)
D Latch (6 min)
D-flip-flop (14 min)
7.2: Sequential Logic Timing Considerations
Sequential Logic Timing (10 min)
7.3: Circuits Based on Sequential Storage Devices
Toggle Flops (12 min)
Ripple Counters (14 min)
Switch Debouncing (20 min)
Shift Registers (3 min)
7.4: Finite State Machine
FSM Introduction & Descripting FSM Behavior (20 min)
FSM Synthesis (29 min)
FSM Design Process Overview (6 min)
FSM Example: Sequence Detector (17 min)
FSM Example: Vending Machine (12 min)
7.5: Counters
Example: 2-bit Binary Up Counter (17 min)
Example: 2-bit Binary Up/Down Counter (8 min)
Example: 2-bit Gray Code Up Counter (7 min)
Example: 2-bit Gray Code Up/Down Counter (7 min)
Example: 3-bit One-Hot Up Counter (7 min)
Example: 3-bit One-Hot Up/Down Counter (6 min)
7.6: FSM Reset Condition
Reset Condition (7 min)
7.7: Sequential Logic Analysis
Functional Analysis of FSMs (9 min)
Timing Analysis of FSMs (15 min)

Chapter 8 - VHDL (Part 1)

8.1: The Process
Process Overview  (26 min)
8.2: Conditional Programming Constructs
If/Then Statements (14 min)
Case Statements (22 min)
Loops (9 min)
8.3: Signal Attributes
Attributes Overview  (6 min)
8.4: Test Benches
Test Bench Basics  (23 min)
Test Bench Report & Assert Statements (26 min)
8.5: Packages
STD_LOGIC_1164 Overview  (23 min)
STD_LOGIC_1164 In VHDL  (9 min)
NUMERIC_STD + Misc Packages  (13 min)
TEXTIO and Writing to External Files  (15 min)
TEXTIO and Reading from External Files (19 min)

Chapter 9 - Behavioral Modeling of Sequential Logic

9.1: Modeling Sequential Storage Devices in VHDL
D-Flip-Flops using a Process  (31 min)
9.2: Modeling Finite-State-Machines in VHDL
Overview of FSMs in VHDL using the 3-Process Approach (20 min)
- FSM Modeling with User-Enumerated State Encoding (PBWC Ex) (15 min)
FSM Modeling with Explicit State Encoding w/ SubTypes (PBWC Ex) (9 min)
9.3: FSM Design Examples in VHDL
Serial Bit Sequence Detector (28 min)
- Vending Machine (15 min)
9.4: Modeling Counters in VHDL
Counters in VHDL w/ 1-Process and Integers/Type-Casts (19 min)
Counters in VHDL w/ Range Checking (25 min)
Counters in VHDL w/ Enables (5 min)
Counters in VHDL w/ Loads (17 min)
9.5: RTL Modeling
- Registers w/ Enables (18 min)
- Shift Registers (11 min)
- Agents on a Multi-Drop Bus (21 min)

Chapter 10 - Memory

10.1: Memory Architecture & Terminology
Architecture & Terminology Overview  (33 min)
10.2: Non-Volatile Memory Technology
Non-Volatile Memory Overview (33 min)
10.3: Volatile Memory Technology
- SRAM (11 min)
DRAM (17 min)
10.4: Modeling Memory in VHDL
Modeling ROM in VHDL (14 min)
Modeling R/W Memory in VHDL (7 min)

Chapter 11 - Programmable Logic

11.1: Programmable Arrays
Programmable Array Overview  (24 min)
11.2: Field Programmable Gate Arrays
FPGA Overview (13 min)

Chapter 12 - Arithmetic Circuits

12.1: Addition
Ripple Carry Adders (RCA)  (28 min)
RCA Timing (8 min)
RCA Structural Design in VHDL (5 min)
Carry Look Ahead Adders (CLA), CLA Timing (22 min)
Behavioral Modeling of Adders in VHDL (15 min)
12.2: Subtraction
Subtraction Overview  (18 min)
12.3: Multiplication
Multiplication Overview (23 min)
12.4: Division
Division Overview (16 min)

Chapter 13 - Computer Systems

13.1: Computer Hardware
Computer System Overview  (12 min)
Computer Hardware Overview  (16 min)
Computer CPU & Memory Details (12 min)
13.2: Computer Software
Opcodes & Operands, Addressing Modes  (16 min)
Instructions Classes: Loads  (23 min)
Instructions Classes: Stores  (11 min)
Instructions Classes: Data Manipulations  (11 min)
Instructions Classes: Branches  (14 min)
13.3: Computer Implementation in VHDL: An 8-Bit Computer Example
Memory System (22 min)
CPU: Data Path (22 min)
CPU: Control Unit - LDA_IMM Instruction (20 min)
CPU: Control Unit - LDA_DIR Instruction (9 min)
CPU: Control Unit - STA_DIR Instruction(16 min)
CPU: Control Unit - ADD_AB Instruction (8 min)
CPU: Control Unit - BRA Instruction (12 min)
CPU: Control United - BEQ Instruction (13 min)
13.4: Architecture Considerations
Von Neumann vs. Harvard (6 min)

Lab Exercises

Lab Exercises (based on Analog Discovery 2 + Altera FPGA Board)

Lab Exercise Workbook - DE0-CV Version (updated 6/29/2019)
Lab Exercise Workbook - DE10-Lite Version (updated 7/2/2020)

Overview Videos

Chapter 1: Analog vs. Digital

Lab 1.1 Overview: Intro to Lab Equipment & Blinking an LED with the AWG (30 min)

Chapter 2: Number Systems

Lab 2.1 Overview: 2-Bit Counter with AWG and Logic Analysis (14 min)

Chapter 3: Digital Circuits & Interfacing

Lab 3.1 Overview: Digital Circuit Operation (26 min)

Chapter 4: Combinational Logic Design

Lab 4.1 Overview: Prime Number Detector using Canonical Forms (+ LED Driver) (26 min)
Lab 4.2 Overview: Prime Number Detector using Minimized Forms (+ Buzzer) (16 min)
Lab 4.3 Overview: 7-Segment Decoder (Discrete) (14 min)

Chapter 5: VHDL (part 1)

Lab 5.1 Overivew: 4-Input, Prime Number Detector (VHDL + FPGA) (35 min)

Chapter 6: MSI Logic

Lab 6.1 Overview: 4-Input, 7-Segment Display Decoder (VHDL + FPGA) (23 min)

Chapter 7: Sequential Logic Design

Lab 7.1 Overivew: 4-Bit Ripple Counter & Switch Debouncing (24 min)
Lab 7.2 Overview: FSM Design, 3-Bit Binary Up/Down Counter (14 min)
Lab 7.3 Overview: 4-bit Binary, Up/Down Counter FSM (VHDL + FPGA) (30 min)

Chapter 8: VHDL (part 2)

Lab 8.1 Overview: 7-Segment Decoder using a Process (9 min)
Lab 8.2 Overview: Design Reuse and Binary Characters on the 7-Segment Display (9 min)

Chapter 9: Behavioral Modeling in VHDL

Lab 9.1 Overview: Ripple Counter (19 min)
Lab 9.2 Overview: Walking 1 FSM (9 min)
Lab 9.3 Overview: Counters w/ 1-Process + 2-to-n Clock Divider (15 min)
Lab 9.4 Overview: BCD Counter + Precision Clock Divider (25 min)

Chapter 10: Memory

Lab 10.1 Overview: Read Only Memory System (5 min)
Lab 10.2 Overview: Read/Write Memory System (18 min)

Chapter 11: Programmable Logic

Lab 11.1 Overview: FPGA Details (19 min)

Chapter 12: Arithmetic Circuits

Lab 12.1 Overview: Signed Adders (4 min)
Lab 12.2 Overview: Unsigned Adders (9 min)

Chapter 13: Computer Systems

Computer Project Overview (15 min)
Computer Project - Part 1: VHDL Shell (31 min)
Computer Project - Part 2: Simulation of 4x Basic Instructions (25 min)
Computer Project - Part 3: FPGA Implementation of Basic Instructions (16 min)
Computer Project - Part 4: Implementation of Additional Instructions (6 min)